A digital data communication protocol uses a data that carries both the data stream and a data clock on a single channel. In this protocol, the receiving circuit includes a clock and data recovery (CDR) circuit which produces a recovered clock, based on a local reference clock that has a frequency close to the clock carried in the data. The receiving circuit uses the recovered clock to set sampling times for sampling the data on the channel. Phase differences between the recovered clock and the data can be detected and used as feedback in the generation of the recovered clock.
Some applications need burst mode operation, i.e. the lock-in time should be within several tens of bits. Traditional burst mode CDR use gated voltage controlled oscillator (GVCO) to achieve instant locking. FIG. 1 illustrates a burst mode CDR according to an embodiment of a prior art. However, the absolute phase alignment with input data may amplify high frequency jitter of input data and degrade timing margin of the CDR. FIG. 2 illustrates an injection lock CDR suitable for burst mode operation with a complicated injection scheme. Both approaches need additional replica of the voltage controlled oscillator based on phase locked loop to control local oscillator frequency.